LMS12JC40 Datasheet | LOGIC Devices Incorporated

DESCRIPTION The LMS12 is a high-speed 12 x 12-bit binatorial multiplier integrated with a 26-bit adder in a single 84-pin package. It is an ideal building block for the implementation of very highspeed FIR filters for video, RADAR, and other similar applications. The LMS12 implements the general form (A- B) + C. As a result, it is also useful in implementing polynomial approximations to transcendental functions. ARCHITECTURE A block diagram of the LMS12 is shown below. Its major features are discussed individually in the following paragraphs. MULTIPLIER The A11-0 and B11-0 inputs to the LMS12 are captured at the rising edge of the clock in the 12-bit A and B input registers, respectively. These registers are independently enabled by the ENA and ENB inputs. The registered input data are then applied to a 12 x 12-bit multiplier array, which produces a 24-bit result. Both the inputs and outputs of the multiplier are in two’s plement format. The multiplication result forms the input to the 24-bit product register. SUMMER The C 25-0 inputs to the LMS12 form a 26-bit two’s plement number which is captured in the C register at the rising edge of the clock. The C register is enabled by assertion of the ENC input. The summer is a 26-bit adder which operates on the C register data and the sign extended contents of the product register to produce a 26-bit sum. This sum is applied to the 26-bit S register. OUTPUT The FTS input is the feedthrough control for the S register. When FTS is asserted, the summer result is applied directly to the S output port. When FTS is deasserted, data from the S register is output on the S port, effecting a one-cycle delay of the summer result. The S output port can be forced to a high-impedance state by driving the OE control line high. FTS would be asserted for conventional FIR filter applications, however the insertion of zero-coefficient filter taps may be acplished by negating FTS. Negating FTS also allows application of the same filter...